Japanese Patent Application No. 2001-165451, filed on May 31, 2001, is hereby incorporated by reference in its entirety.
The present invention relates to a nonvolatile semiconductor memory device including memory cells, each of the memory cells having two nonvolatile memory elements and being controlled by one word gate and two control gates.
As one type of nonvolatile semiconductor memory device, a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor or Metal-Oxide-Nitride-Oxide-Substrate) device is known. In the MONOS nonvolatile semiconductor memory device, a gate insulating layer between a channel and a gate is formed of a laminate consisting of a silicon oxide film, silicon nitride film, and silicon oxide film. Charges are trapped in the silicon nitride film.
The MONOS nonvolatile semiconductor memory device is disclosed in literature (Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123). This literature discloses a twin MONOS flash memory cell including two nonvolatile memory elements (MONOS memory cells) controlled by one word gate and two control gates. Specifically, one flash memory cell has two charge trap sites.
In order to drive the twin MONOS flash memory cell, two bit lines, one word line, and two control gate lines are necessary.
Of these interconnects, two bit lines and two control gate lines are generally wired in the column direction. However, it is difficult to provide four interconnects (two bit lines and two control gate lines) within the width of a plurality of memory cells in one column using the same metal interconnect layer even in the case of using a photolithographic process with a minimum line and space width.
Therefore, the wiring space must be secured by increasing the width of the memory cells in one column. However, this causes a decrease in the degree of integration of the memory cells, whereby it is impossible to deal with a recent increase in the capacity of the nonvolatile semiconductor memory device.
The present invention may provide a highly integrated nonvolatile semiconductor memory device in which each memory cell has two trap sites.
The present invention may also provide a nonvolatile semiconductor memory device capable of securing the degree of margin and freedom for the arrangement of metal interconnects by extending impurity layers to provide bit lines without metal interconnects as the bit lines.
According to one aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising: a memory cell array region in which a plurality of memory cells are arranged in first and second directions intersecting each other, each of the memory cells having two nonvolatile memory elements and being controlled by one word gate and two control gates; and a select region disposed adjacent to the memory cell array region in the first direction.
The memory cell array region includes: a plurality of sub bit lines formed of impurity layers extending to the select region in the first direction, and provided on both sides of the memory cells arranged in the first direction; a plurality of control gate lines extending in the first direction, the number of the control gate lines being twice the number of the sub bit lines; a plurality of word lines extending in the second direction; a plurality of main bit lines extending in the first direction and provided within the select region and the memory cell array region, the number of the main bit lines being smaller than the number of the sub bit lines; and a sub bit select circuit which is provided in the select region and selectively connects the sub bit lines with the main bit lines.
In this aspect of the present invention, the plurality of sub bit lines are formed of the impurity layers extending from the memory cell array region to the select region. Therefore, metal interconnects for backing the plurality of sub bit lines are unnecessary. As a result, a large number of metal interconnects can be omitted for the sub bit lines. This produces a surplus of space which can be assigned to other metal interconnects, whereby the degree of freedom for the metal interconnects can be increased.
Moreover, since the number of main bit lines can be less than the number of sub bit lines, a surplus of wiring space is produced for a layer in which the main bit lines are disposed, whereby the degree of freedom relating to the wiring can be increased.
Therefore, there is no need to decrease the degree of integration in order to secure space for the metal interconnects even if one memory cell has two trap sites, whereby a highly integrated nonvolatile semiconductor memory device can be provided.
In this nonvolatile semiconductor memory device, the select region may include first and second select regions disposed on both sides of the memory cell array region in the first direction.
The degree of freedom for each interconnect is further increased by dividing the select region to which the plurality of sub bit lines and the plurality of sub control gate lines extend in two.
In this nonvolatile semiconductor memory device, an even-numbered sub bit line among the sub bit lines may extend to the first select region; and an odd-numbered sub bit line among the sub bit lines may extend to the second select region.
This enables circuits for selectively connecting the sub bit lines with the main bit lines to be separately disposed in the first and second select regions based on odd numbers and even numbers, whereby the circuit layout is simplified.
Specifically, the first select region may include an even-numbered sub bit select circuit which selectively connects the even-numbered sub bit line with even-numbered main bit line among the main bit lines; and the second select region may include an odd-numbered sub bit select circuit which selectively connects the odd-numbered sub bit line with odd-numbered main bit line among the main bit lines.
The memory cell array region may include a plurality of common connection sections each of which connects two of the control gate lines disposed on both sides of each of the sub bit lines, at one end portion of the memory cell array region on the side opposite to the side on which the sub bit line between the two of the control gate lines extends to the select region. In this case, a plurality of sub control gate lines may connect the common connection sections to the select region, the number of the sub control gate lines being equal to the number of the sub bit lines.
A plurality of main control gate lines may be provided to extend in the first direction in the select region and the memory cell array region, and the number of the main control gate lines may be smaller than the number of the sub control gate lines. In this case, the select region may include a sub control gate select circuit which selectively connects the sub control gate lines with the main control gate lines.
This enables the number of main control gate lines to be smaller than the number of sub control gate lines, whereby a surplus of wiring space is produced because the total number of interconnects decreases even if the main control gate lines are disposed in the same layer as the main bit lines.
Two of the control gate lines on both sides of the odd-numbered sub bit line may be connected to each other by an odd-numbered common connection section of the common connection sections at one end in the first direction; and two of the control gate lines on both sides of even-numbered sub bit line may be connected to each other by an even-numbered common connection section of the common connection sections at the other end in the first direction.
By alternately providing the odd-numbered and even-numbered common connection sections on opposite ends of the memory cell array region in the first direction, the odd-numbered and even-numbered sub control gate lines connected to the common connection sections can be disposed in opposite directions.
Specifically, the odd-numbered common connection section may be connected to an odd-numbered sub control gate line extending to the first select region.
The even-numbered common connection section may be connected to an even-numbered sub control gate line extending to the second select region.
This enables the length of the sub control gate lines which connect the memory cell array region with the select region to be minimized.
In this case, the first select region may have an odd-numbered sub control gate select circuit which selectively connects the odd-numbered sub control gate line to an odd-numbered main control gate line. The second select region may have an even-numbered sub control gate select circuit which selectively connects the even-numbered sub control gate line to an even-numbered main control gate line.
Since the control gate select circuits can be dispersed in the first and second select regions in this manner, the circuit layout can be simplified.
If a memory block is formed of the memory cell array region and the select region, a plurality of the memory cells may be arranged in the first direction. This enables an increase in the storage capacity of the nonvolatile semiconductor memory device. Moreover, since the length of the sub control gate lines and the sub bit lines can be decreased, the wiring capacitance can be reduced. Furthermore, since data can be collectively erased in the block unit, the erase unit can be reduced in comparison with the case of erasing data over the entire memory.
In this case, a main bit line driver which drives the plurality of main bit lines may be provided on one end of the arranged memory blocks in the first direction.
This enables the plurality of main bit lines to be shared by the plurality of memory blocks, and the main bit line driver to be shared by the plurality of memory blocks.
Moreover, a main control gate line driver which drives the plurality of main control gate lines may be provided on the other end of the arranged memory blocks in the first direction.
This enables the plurality of main control gate lines to be shared by the plurality of memory blocks, and the main control gate line driver to be shared by the plurality of memory blocks.
A word line driver which drives the word lines may be provided on either side of the arranged memory blocks in the second direction. In order to further increase the storage capacity of the nonvolatile semiconductor memory device, the plurality of memory blocks may be disposed on both sides of the word line driver in the second direction.
The plurality of sub control gate lines may form a first metal interconnect layer. A second metal interconnect layer perpendicular to the first metal interconnect layer may be connected with the plurality of word lines extending in the second direction.
A third metal interconnect layer perpendicular to the second metal interconnect layer may be used as the main bit lines and the main control gate lines.
Since an excessive increase in the number of interconnects can be prevented in the first to third layers, the degree of margin of wiring can be secured.
Two nonvolatile memory elements in each memory cell of the nonvolatile semiconductor memory device according to one aspect of the present invention may has an ONO film consisting of an oxide film (O), nitride film (N), and oxide film (O) as a charge trap site. However, other types of structures may be employed.